1. Field of the Invention
The present invention relates to integrated circuits and, more specifically, to a power supply used in memory circuits.
2. Description of the Prior Art
Very large scale integrated circuit (VLSI) chip designs often contain a variety of circuit types to meet the functional requirements of the product. These include static CMOS circuits for control and dataflow, six-transistor cell-based SRAM arrays for high-density storage, analog circuits for clock phase alignment and other non-digital functions. This variety of circuit design styles, and their interaction with the wafer manufacturing technology, often requires these circuits to operate under different voltage supply levels. At a minimum, a requirement for lower power supply noise or less variation (tolerance) often forces the system designer to supply more than one power supply so that a higher supply (e.g. AVDD) than can be regulated on-chip.
Several existing integrated circuits include logic circuits and memory arrays. The logic circuits may be able to detect special modes where a lower voltage may be applied to both the logic circuits and the memory arrays. Typically, such modes involve lowering the clock frequency of the integrated circuit. For example, when a processor is in an idle state, it may be desirable to enter a low frequency state. In such a state, the voltage of the power supply to the logic circuits and memory arrays may be reduced, corresponding to the lower demand for current flow in the circuits. Lowering the voltage from the power supply will decrease heat dissipation and improve the computing power per watt per unit area ratio (which is one measure of overall performance) of the integrated circuit. In another example, an integrated circuit may be used with an entertainment device, such as a video game player. In one mode, the video game player may used to play a DVD and it is desirable to reduce noise generated by the video game player by slowing (or disabling) its fan. This may be accomplished in part by reducing the power supply voltage to the logic circuits and memory arrays in the integrated circuits, thereby reducing the heat dissipated by such circuits.
One type of variable power supply for logic and arrays enables “tuning” of the supply voltage to optimize frequency and power. This technique (called “adaptive power supply”) allows slow chips with low DC leakage to be operated at a higher supply voltage than are fast parts with high leakage. This allows a larger fraction of the functionally correct circuits to meet the frequency and power limits of the product. The variable power supply (VDD) is typically supplied through an off-chip voltage regulator since an on-chip voltage regulator capable of supplying power to nearly the entire chip would be prohibitively large in area. The external voltage regulator (VREG) is controlled by Voltage Identification (VID) buss (typically 1–5 bits) which are generated by on-chip logic. The VID setting is typically determined at manufacturing test, during which tests are performed to characterize the frequency and power properties of the individual chip, and stored in non-volatile memory (e.g., electronic fuses or EPROM). The on-chip logic bases the VID setting on this data or other conditions (e.g., if the chip is under power-up, low-power mode, or other conditions at which the programmed VID setting is not appropriate). On the same chip, it remains useful to supply a second separate power supply to other circuits (e.g., analog circuits).
More recent wafer manufacturing technologies have introduced increased variability in the properties of devices. This variability has especially impacted the design of SRAM-cell based memory arrays. The balance between cell read/write performance and cell stability is becoming more and more difficult to maintain. Both cell stability and read/write performance can impact product manufacturing yields. Improving the performance of the cell by making it larger results in a greater area of the chip dedicated to arrays and a larger, more expensive chip. A higher supply voltage on the cell array improves the margin in both performance and stability. However, use of a higher supply for all circuits on a VLSI chip somewhat negates the power savings benefit of more advanced technologies that allow equivalent or improved performance at lower supply voltages. Therefore, a compromise is to supply static logic with a lower supply voltage (VDD) and arrays with a second somewhat-higher supply (VCS). The advantage of the adaptive power supply technique described earlier is lost unless the core voltage (VDD) and the array voltage (VCS) are varied. In addition, since the arrays and logic must communicate on-chip, it becomes difficult to design a chip such that the arrays are on a fixed, higher supply while the logic is on a varying (higher or lower) supply.
As shown in FIG. 1, a typical existing integrated circuit chip 100 includes input/output (I/O) circuitry 112, logic circuitry 114, array circuitry 116 and analog circuitry 118, such as clock phase alignment (PLL) circuits. The I/O circuitry 112 is supplied by an off-chip power source (IOVDD) and the analog circuitry 118 is supplied by another off-chip power source (AVDD), the power from which is regulated by a voltage regulator 124. The logic circuitry 114 and the array circuitry 116 are driven by a common power source (V), the power from which is regulated by a first off-chip voltage regulator 120 for the logic circuitry 114 and a second off-chip voltage regulator 122 for the array circuitry 116. The logic circuitry 114 provides a first voltage identification feedback signal (VID_L) to the logic voltage regulator 120 and a second voltage identification feedback signal (VID_A) to the array voltage regulator 116. The VID_A signal ensures that the array voltage regulator 116 tracks the voltage level output from the logic voltage regulator 120. Thus, when the logic voltage regulator 120 enters a reduced voltage state, the array voltage regulator 116 will enter a similar reduced voltage state, possibly with a voltage offset (e.g., 100 mV) that meets the operating requirements of the array circuit.
Providing separate power supplies at the system level is costly and therefore avoided where possible, but in the case of critical circuits such as clock phase alignment (PLL) the benefit of separate supplies is often worth the cost.
Therefore, there is a need for a power supply in which both the core (VDD) and array (VCS) supplies track each other employing on-chip voltage regulators.